In the prior art practice, a memory module is used including a plurality of memory chips mounted on a printed circuit board in order to facilitate changing a memory arrangement (capacity, bit configuration or the like) in an information processing system such as a personal computer, work station, or the like. There are a variety of memory modules. For example, U.S. Pat. No. 4,656,605 discloses a SIMM (Single Inline Memory Module) containing nine memory chips mounted on a rectangular printed circuit board having thirty terminals on a side.
A SIMM containing memory chips mounted on a rectangular printed circuit board which is formed with a card edge connector including 30 or 72 pins on a side, a DIMM (Dual Inline Memory Module) containing memory chips mounted on a printed circuit board which is formed with a dual surface card edge connector having 168 pins on a side, or a memory module such as a memory card of a size comparable to a credit card and in which memory chips are mounted are commonly in use.
A trend toward a higher level of integration, a greater capacity and a higher level of functionality is increasing from year to year in memory chips which are used in such memory modules. Accordingly, a technical requirement imposed upon such a memory chip during its manufacture is becoming stringent. Since it is premised that such a memory chip is generally used as a memory structured as N words (where N is a power of 2 such as 256 kilowords (2.sup.18), 1 megawords (2.sup.20) or the like).times.I bits, if there is a defect even in one of the bits, the resulting memory is not capable of storing N words.times.I bits information, and thus becomes a faulty component.
To accommodate for this, it is known to provide a memory chip with redundant bits, and in the manufacture of the memory chip, defective bits are replaced with redundant bits by switching of switching circuit or by breakage of fuses. With such a memory chip, the presence of a defective bit or bits is detected during the manufacture, and the detected defective bit or bits are replaced by redundant bits. In this manner, a memory chip containing a defective bit or bits can be converted into a non-faulty component, thus improving the yield of memory chips.
However, if an arrangement for replacement of defective bits by redundant bits is provided, an external switching through a switching circuit cannot take place after the memory chip is packaged, because a control terminal which is used in controlling a switching operation by a switching circuit is generally not connected to the outside of the package. Thus, if the presence of defective bits in the memory chip is found subsequent to packaging, the memory chip cannot be repaired even though the remedy of such defect is within the allowance that can be achieved through the switching operation.
While it is difficult to repair such a defective memory chip when it is treated as a single component, a memory chip containing a certain number of defective bits can be used when a plurality of memory chips mounted on a printed circuit board constitute the memory module, by avoiding the use of defective bits through a switching circuit which is provided on the printed circuit.
In a memory module, it is difficult to provide a complex switching circuit on account of the restriction of the space on the printed circuit board on which the memory chips are mounted. Accordingly, a simple switching circuit which comprises a wiring pattern printed on the printed circuit board is used. Such a switching circuit is arranged so that for a memory chip having a defect in a particular one of four bits in one word, for example, input/output terminals associated with three non-defective bits are connected to input/output terminals of the memory module.
However, when the memory module is constructed with a plurality of memory chips in which defects occur at random positions, the use of a switching circuit which comprises such a wiring pattern can not provide a remedy since a different wiring pattern must be provided for each combination of the locations of defects in the memory chips.
For this reason, the prior art practice has been to construct a memory module using only those memory chips which have defects at an identical bit location. This enables the number of combinations of the locations of defects in the memory chips to be reduced, and hence the variety of wiring patterns can be reduced as compared with the occurrence of a random combination of defect locations.
However, to follow such scheme, the memory chips must be classified according to the location in which a defect occurred in the memory chip and the printed circuit board must be changed for each variety of the classified memory chips for manufacturing purpose, thus degrading the manufacturing efficiency.